module FetchFinishedGenerator(icode, pc, counter, icode_d, icode_e, finished, hold);
input [3:0] icode;
input [3:0] icode_d;
input [3:0] icode_e;
input [31:0] pc;
input [1:0] counter;

output reg hold;
output reg finished;

wire is_align = !pc[0];

always @(*) begin
	if(icode == 1 || icode_d == 9 || icode_e == 9) begin
		hold = 1;
	end else begin
		hold = 0;
	end
end


always @(*) begin
	if(counter == 0)begin
		if(is_align) begin
			case(icode)
				3,4,5,7,8: finished = 0;
				default: finished = 1;
			endcase
		end else begin
			case(icode)
				2,6,10,11,3,4,5,7,8: finished = 0;
				default: finished = 1;
			endcase
		end
	end else if(counter == 1) begin
		if(is_align) begin
			case(icode)
				3,4,5,7,8: finished = 0;
				default: finished = 1;
			endcase
		end else begin
			case(icode)
				3,4,5,7,8: finished = 0;
				default: finished = 1;
			endcase
		end
	end else if(counter == 2) begin
		if(is_align) begin
			finished = 1;
		end else begin
			case(icode)
				3,4,5: finished = 0;
				default: finished = 1;
			endcase
		end
	
	end else begin
		finished = 1;
	end
end

endmodule